A DMOS (Double diffused MOS) transistor is a type of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that uses two sequential diffusion steps aligned to a common edge to form a channel region of the transistor. DMOS transistors are often high voltage, high current devices, used either as discrete transistors or as components in power integrated circuits. DMOS transistors can provide high current per unit area with a low forward voltage drop.
One particular type of DMOS transistor is a so-called trench DMOS transistor in which the channel is present on the sidewall of a trench, with the gate formed in the trench, which extends from the source towards the drain. The trench, which is lined with a thin oxide layer and filled with polysilicon, allows less constricted current flow than the planar vertical DMOS transistor structure and thereby provides lower values of specific on-resistance.
There exists a need to easily fabricate a trench DMOS transistor with variable-thickness gate trench oxides strategically placed at different portions inside the trench to maximize device performance. For example, a thinner gate oxide is preferred at the upper portion of the trench to maximize channel current. By contrast, a thicker gate oxide is desired at the bottom portion of trench to support higher gate-to-drain breakdown voltage.
U.S. Pat. No. 4,941,026 discloses a vertical channel semiconductor device including an insulated gate electrode having a variable thickness oxide, but does not illustrate how to make such a device.
U.S. Pat. No. 4,914,058 discloses a process for making a DMOS, including lining a groove with a nitride to etch an inner groove having sidewalls extending through the bottom of the first groove, and lining the inner groove with a dielectric material by oxidation growth to obtain increased thickness of the gate trench dielectric on the sidewalls of the inner groove.
US publication No. 2008/0310065 discloses a transient voltage suppressing (TVS) circuit with uni-directional blocking and symmetric bi-directional blocking capabilities integrated with an electromagnetic interference (EMI) filter supported on a semiconductor substrate of a first conductivity type. The TVS circuit integrated with the EMI filter further includes a ground terminal disposed on the surface for the symmetric bi-directional blocking structure and at the bottom of the semiconductor substrate for the uni-directional blocking structure and an input and an output terminal disposed on a top surface with at least a Zener diode and a plurality of capacitors disposed in the semiconductor substrate to couple the ground terminal to the input and output terminals with a direct capacitive coupling without an intermediate floating body region. The capacitors are disposed in trenches having an oxide and nitride lining.
A difficulty arises during polysilicon gate backfill in the trench if a thick oxide is uniformly formed in the trench, producing a higher trench aspect ratio (ratio of depth A to width B) as shown in the prior art. By way of example, FIGS. 1A-1D are cross-sectional views illustrating a prior art method of forming a single gate of the prior art. As shown in FIG. 1A, a trench 106 is formed in a semiconductor layer 102. A thick oxide 104 is formed on the bottom and sidewalls of the trench 106 which increases its aspect ratio A/B. Polysilicon 108 is in-situ deposited into the trench 106. Due to the high aspect ratio of the polysilicon deposition, a keyhole 110 tends to form as shown in FIG. 1B. As shown in FIG. 1C, the poly 108 is etched back followed with an isotropic high temperature oxidation (HTO) oxide etch as shown in FIG. 1D, throughout which a portion of the keyhole 110 remains.
FIG. 2 is a cross-sectional view of a current shield gate trench (SGT) device 200 having a shield poly gate with an Inter-Poly Oxide (IPO) 202 between a first polysilicon structure that forms a gate 204 and a second polysilicon structure 206 that acts as a conductive shield. According to one prior art process, such a structure is formed by a process that involves two etch-back steps (of the polysilicon layer 206 and of the IPO oxide layer 202) in forming the IPO 202 between the two polysilicon structures 204, 206. Specifically, the polysilicon that forms the shield 206 is deposited in the trench and etched back and HDP oxide is formed on the shield 206 and etched back to make room for deposition of the polysilicon that forms the gate structure 204. This approach has the drawback of poor IPO thickness controllability across wafer. The IPO thickness depends on two independent and unrelated etch-back steps, which could cause non-uniform and local thinning of IPO thickness due to either under etch-back of Poly or over etch-back of Oxide or a combination of both.
Also, in the methods discussed above the thickness of the gate trench dielectric on the thick portion of the side wall versus the thickness at the bottom of the trench are linked together. One thickness cannot be altered without affecting the other thickness.
It is within this context that embodiments of the present invention arise.